This invention can be used in data processing devices, as well as in automatic and telemechanical devices and in general-purpose computer systems.
There is known in the art a microcomputer processor (cf., U.S. Pat. No. 4,016,546, class 340/172.5, Int. Cl. G 06 F 9/20, published in 1975) comprising an address line, a data bus, registers connected therewith, an arithmetic-logical device, and a control unit connected to the registers and to the arithmetic-logical device. Said prior art processor lacks means for implementing algorithms of symbolic processing at the microprogramming level, which affects the overall performance of the processor.
Closest of all to the herein disclosed microcomputer processor, as regards its technical essence, is a microcomputer processor (cf., Mark I. Sebern, A Minicomputer-Compatible Microcomputer System: The DEC LSI-11, Proceedings of the IEEE, Vol. 64, No. 6, June 1976) comprising a scratch-pad storage for storing digital data in the course of the microcomputer processor operation, an arithmetic-logical unit for digital data conversion, an interface unit for digital data exchange, all of said units interconnected by means of an intraprocessor data bus. The latter prior art microcomputer processor further comprises a microprogram unit for control over the execution of digital data conversion and exchange operations in the microcomputer processor, a first input of said microprogram unit being connected to the intraprocessor data bus while its output is connected to control inputs of the scratch-pad storage, an arithmetic-logical unit and an interface unit, and a processor status register for storing the arithmetic operation code. The input of the processor status register is connected to the output of the arithmetic-logical unit while its output is connected to a second input of the microprogram unit. The control input of the processor status register is connected to the output of the microprogram unit.
In this latter prior art microcomputer processor, provision is made for a microinstruction format for character-by-character operation and for conditional jump microinstruction format. However, the microinstruction field for character-by-character operation, as well as the microinstruction field to be used for conditional jumps, is limited to eight bits, and operations with 16-bit words are executed over two or more computer cycles. The expansion of the microinstruction field for characters would lead to a considerable increase in the volume of the microprogram unit. Therefore, the speed of execution of instructions for symbolic data processing is not high. Moreover, said prior art processor is incapable of processing binary-coded-decimal numbers at the microprogramming level, this presenting a limitation of its functional capabilities.